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Tech Tuneup:
Nano VLSI
University of Minnesota
Electrical & Computer Engineering Dept
Digital Technology Center
June 26-28, 2006
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Summary |
The Department of Electrical and Computer Engineering (ECE) is hosting the Tech Tuneup: Nano VLSI Design course at the University of Minnesota on June 26-28, 2006. This year Tech Tuneup will focus on the applications and problem areas associated with the very near future nano VLSI generation. Topics that will be covered during the 3-day course include:
- Advanced digital CMOS circuit design
- Advanced CAD for analog, RF and mixed-signal systems
- Digital design, verification and applications
- Architectural design issues for reliable computing
- Current FPGA architectures and computer-aided design (CAD)
- Tolerating process variations through design and CAD in sub-100nm circuits
- Nanoscale CMOS (<100nm) analog interface design
- Process issues for nanoscale CMOS
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Venue |
Tech Tuneup will be held at:
Nearest parking ramps:
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| Registration |
 The registration fee is $900, and includes lunch and coffee during the three days of the course.
Click here to register for the course.
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| Schedule |
Monday, 26 June, 2006
| 9:00-10:30 |
Tolerating process variations through design and CAD in sub-100nm circuits
Sachin Sapatnekar
ECE Dept, Univ of Minnesota |
| 10:30-10:45 |
Coffee Break |
| 10:45-12:15 |
Current FPGA architectures & CAD
Kia Bazargan
ECE Dept, Univ of Minnesota |
| 12:15-1:45 |
Lunch & Posters |
| 1:45-2:45 |
The Structured ASIC landscape
Scott A. Peterson
LSI Logic, Minneapolis |
| 2:45:3:00 |
Coffee Break |
| 3:00-4:30 |
Advanced CAD for analog, RF and mixed-signal systems
Jaijeet Roychowdhury
ECE Dept, Univ of Minnesota |
| 4:30-5:30 |
Open House |
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Tuesday, 27 June, 2006
| 9:00-10:30 |
Architectural design issues for reliable computing
David Lilja
ECE Dept, Univ of Minnesota |
| 10:30-10:45 |
Coffee Break |
| 10:45-12:15 |
Digital design, verification and applications
Gerald Sobelman
ECE Dept, Univ of Minnesota |
| 12:15-1:45 |
Lunch & Posters |
| 1:45-2:45 |
Ionizing radiation effects in submicron microelectronics
AJ KleinOsowski
IBM Austin Research Center |
| 2:45:3:00 |
Coffee Break |
| 3:00-4:30 |
Process issues for deep submicron CMOS
Steve Campbell
ECE Dept, Univ of Minnesota |
| 4:30-5:30 |
Open House |
Wednesday, 28 June, 2006
| 9:00-10:30 |
Designing deep submicron (<100nm) analog circuits
Ramesh Harjani
ECE Dept, Univ of Minnesota |
| 10:30-10:45 |
Coffee Break |
| 10:45-12:15 |
Advanced digital CMOS circuit design
Chris Kim
ECE Dept, Univ of Minnesota |
| 12:15-1:45 |
Lunch & Posters |
| 1:45-2:45 |
High speed serial I/O
David Tetzlaff
Xilinx Inc., Minneapolis |
| 2:45:3:00 |
Coffee Break |
| 3:00-4:30 |
Performance scalability in non-scalable nanometer technology
Jean-Oliver Plouchart
IBM T.J. Watson Research Ctr |
| 4:30-5:30 |
Open House |
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| Why You Should Register! |
| As the feature sizes of integrated circuits go below 100nm (i.e., into the "nanometer regime"), VLSI design is undergoing a transformation, affecting all aspects of circuit design and manufacturing, ranging from the process level to the circuit level to the architectural level. Traditional barriers between these levels of abstraction are falling apart, and it is important for tomorrow's professionals to have a complete view of all these aspects. Tech Tuneup will survey these issues to provide a comprehensive view of the latest developments in the field. The course consists of 12 segments, taught by industry experts and faculty from the University of Minnesota.
This year's short course is specifically targeted towards continuing education for industry professionals. If you are interested in learning more, and you recognize that the only constant in the world of technology is change, Tech Tuneup is just right for you!
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| Contact |
Phone: (612) 625-2855 (Josette Barness)
Fax: 612-625-4583
Email: techtuneup@ece.umn.edu |
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