Technical POC:
Keshab K. Parhi
Professor, Dept. of Electrical & Computer Engineering
Univ. of Minnesota
Minneapolis, MN 55455
Tel: 612-624-4116
Fax: 612-625-4583
Email: parhi@ee.umn.edu
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1. SIGNIFICANT ACCOMPLISHMENTS
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1.1: Area-Efficient Parallel Decoding Schemes:
Turbo decoders inherently have a low speed due to their iterative decoding. The conventional parallel decoding scheme proposed in 1998 can achieve many times speed-up at the expense of an increase in memory size and latency. By combining the sliding block algorithm and the conventional parallel decoding scheme, the extra memory requirement and the extra latency are both reduced. However, the number of computation units is still large. An area-efficient pipelined parallel decoding scheme is developed in this work. It can resolve all of above problems at the expense of a small increase in the complexity of the control circuits. Hybrid pipelined parallel decoding schemes can achieve various trade-off's. They can be better choices for some applications.
1.2 Short Frame Turbo Codes:
We have developed a short frame Turbo coding scheme in which the k-1 CRC bits can be embedded in the trellis states. By reducing the k-1 tail bits and CRC bits and embedding the k-1 CRC bits, a coding gain of 0.75 dB for length 49 short frame Turbo codes is achieved. The coding and decoding scheme has been successfully tested over both AWGN and Rayleigh flat fading channels.
1.3 QRD-RLS Adaptive Filters:
The single-state-update parallel processing architecture has been developed for block weight-update for the standard and the extended QRD-RLS adaptive filters, where a slowly changing non-stationary process is tracked. With this architecture, deep pipelining is avoided for increasing system throughput. Thus, pipelining overhead is saved and a linear increase in power consumption is achieved instead of the square increase in a pipelined processing architecture. Moreover, when the pipelining level and the power consumption are dominant constraints, this architecture can lead to an implementation of much smaller area through the folding transformation.
1.4 Word-Level Transition Activity:
The model for estimating word-level transition activity has been improved. The improved model is simpler in that the bit probability is linearly modeled. The other improvements include refined formulae for the break-point and for computing upper-bit temporal correlation. The mean and the standard deviation of estimation errors over a group of ARMA signals are -0.51% and 2.59% respectively for two's complement representation, or -1.28% and 2.31% respectively for sign-magnitude representation.
A model for estimating the variance of word-level transition activity was developed by using the spatial correlation of bit-level transition activity. The mean and the standard deviation of estimation errors are 1.25% and 3.07% respectively for two's complement representation, or -3.58% and 4.27% respectively for sign-magnitude representation. Thereafter, the power grid noise strength can be determined with the knowledge of this variance.
2. Next Period Activities
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We'll be working on Turbo multiuser detector using interference cancellation.
We plan to develop an optimum hardware architecture for xDSL/cable modem. The focus will be on parts of the OFDM line coding and forward error correcting. The optimum criteria are performance, area, power consumption, power density and power grid noise. The expected achievement will provide a complete solution for chip designs at all levels from algorithm, architecture and scheduling/mapping.
3. Documentation:
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B. Sahoo, M. Kuhlmann and K.K. Parhi, "A Low-Power Correlator", Proc. of 2000 Great Lakes Symposium on VLSI, Evanston, IL, pp. 153-155, March 2000