Technical POC:
Keshab K. Parhi
Professor, Dept. of Electrical & Computer Engineering
Univ. of Minnesota
Minneapolis, MN 55455
Tel: 612-624-4116
Fax: 612-625-4583
Email: parhi@ee.umn.edu
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1. SIGNIFICANT ACCOMPLISHMENTS
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1. New CORDIC Algorithm and Architecture:
CORDIC (COordinate Rotation DIgital Computer) is an iterative algorithm for the calculation of the rotation of a two-dimensional vector, in linear, circular or hyperbolic coordinate systems, using only add and shift operations. Two main objectives have been achieved.
First, we developed a new CORDIC algorithm and architecture for the rotation mode in which the rotation dircetions of every micro-rotation can be precomputed. Hence, the angle remainder does not require any sign check to determine the new rotation direction. By using most-significant digit first adder, a very fast implementation with a latency of 1.5n+2 full-adders can be obtained, where n represents the word-length of the operands. Note that the time delay for the final multiplication by the constant scale factor is not yet included. The implementation is suitable for word-length up to 54 bits and results in a speed improvement of about 20%. Furthermore, a constant scale factor is maintained leading to a regular implementation. Nevertheless, the area for the rotation mode implementation increases by about 20%.
Second, we developed an algorithm and architecture for the shared implementation of CORDIC rotation and vectoring mode for signal processing applications. Like in the pure rotation mode, the directions of the micro-rotations can be precomputed. However, using most-significant digit first adders and multipliers, the computation can be performed in parallel to the actual CORDIC iteration. This leads to an overall critical path of 1.5n+4 full-adders. This corresponds to a speed-up of about 50% to previous reported shared CORDIC implementations. Note that the time delay for the final multiplication by the constant scale factor is not yet included. Nevertheless, the area for the shared implementation increases by about 45% due to a ROM and multipliers to compute the direction of the micro-rotation in parallel to the CORDIC iterations. The implementation is suitable for word-length up to 19 bits with a reasonable ROM size.
2. Low-Power Viterbi Coder:
The increasing demand for portable computing has elevated power consumption to be one of the most critical design parameters. Specifically, as the bit-rate of the next generation wireless communication is increased dramatically, a low power viterbi decoder design is undoubtedly necessary. In particular, we are investigating use of dynamic transformations to optimize the power consumption of convolutional decoders. Power dissipation models of ACS units and memories are being derived. The whole problem is modeled as a constraint optimization problem.
3. Digit-Serial FPGA for DSP Applications
A set of digit-serial benchmark circuits were implemented using Xilinx FPGAs. These include arithmetic functions such as adder/subtractors, shift-registers and multipliers as well as signal processing functions such as inverted-form and canonical-form FIR filters. The digit-serial FIR filters were implemented using both digit-level and bit-level pipelining methods. A performance analysis shows that the bit-level pipelined digit-serial FIR filter, with a digit-size of 4 bits, has a 51% smaller area-time product than that of a comparable bit-parallel implementation. We have optimized the circuit-level design of the digit-serial logic block (DLB) for our custom-designed digit-serial FPGA. Novel pass-transistor exclusive-or and multiplexer circuits have been used to implement the basic logic module of the DLB. Also, a glitch-free true-single phase clocked design was used for the D-type flip-flops. The new DLB core has a 20% smaller area and a 15% smaller delay than our previous circuit implementation.
4. Elliptic Curve Cryptosystem Implementations:
In the hardware architecture of the elliptic curve cryptosystem coprocessor, certain components, including those of the arithmetic units, are not busy at all times during each computation period. Therefore, they are candidates for dynamic run-time reconfiguration. This idea is currently under investigation.
2. NEXT PERIOD ACTIVITIES
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CORDIC work will be directed towards development of the algorithm for vectoring mode. Low-power circuit implementation will also be investigated. Scheduling approaches to implement orthogonal RLS adaptive filters and equalizers using CORDIC building blocks with low power consumption will be investigated. Various CORDIC algorithms will be compared by prototyping using Xilinx FPGA systems.
Finite word length simulations for low power Turbo coders will continue.
Efforts to reduce power consumption of Viterbi coders will continue.
Implementation of efficient radix-4 FFT approaches based on a combination of feed-forward and feedback commutators continues. This approach will lead to lower memory and higher hardware utilization efficiency.
We will continue to finalize the physical layout structure of the DS-FPGA chip. A prototype DS-FPGA chip will be submitted to MOSIS for fabrication.
We will also continue to evaluate various implementations of elliptic curve cryptosystems on commercial FPGA devices.
3. Documentation:
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Y.-N. Chang, J.H. Satyanarayana and K.K. Parhi, "Systematic Design of High-Speed and Low-Power Digit-Serial Multipliers", IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 45(12), pp. 1585-1596, Dec. 1998
J.H. Satyanarayana and K.K. Parhi, "Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation", Accepted for IEEE Trans. on VLSI Systems
J. Ma, K.K. Parhi and E.F. Deprettere, "Annihilation-Reordering Look-Ahead Pipelined CORDIC Based RLS Adaptive Filters and Their Application to Adaptive Beamforming", Submitted to IEEE Trans. on Signal Processing, Jan. 1999
J. Ma, K.K. Parhi, G.J. Hekstra and E.F. Deprettere, "Efficient Implementations of Pipelined CORDIC Based IIR Digital Filters using Fast Orthonormal Micro-rotations", Submitted to IEEE Trans. on Signal Processing, March 1999
J.H. Satyanarayana and K.K. Parhi, "Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation", Proc. of 9th Great Lakes Symp. on VLSI, March 1999, Ann Arbor, MI
H. Suzuki, Y.N. Chang and K.K. Parhi, "Low-Power Bit-Serial Viterbi Decoder for Next Generation Wide-Band CDMA Systems", Proc. of 1999 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Phoenix, March 1999
H. Suzuki, Y.N Chang and K.K. Parhi, "256 States Low-Power Bit-Serial Viterbi Decoder for Next Generation Wireless Applications", Proc. of 1999 IEEE Customs Integrated Circuits (CICC) Conference, San Diego, May 1999
J. Ma, K.K. Parhi and E.F. Deprettere, "Derivation of Parallel and Pipelined Orthogonal Filter Architectures via Algorithm Transformations", Proc. of 1999 IEEE Int. Symp. on Circuits and Systems, Orlando, June 1999
S. Summerfield, Z. Wang and K.K. Parhi, "Area-Power-Time Efficient Pipeline-Interleaved Architectures for Wave Digital Filters", Proc. of 1999 IEEE Int. Symp. on Circuits and Systems, Orlando, June 1999
Z. Chi, J. Ma and K.K. Parhi, "Pipelined QR Decomposition Based Multi-Channel Least Square Lattice Adaptive Filter Architectures", Proc. of 1999 IEEE Int. Symp. on Circuits and Systems, Orlando, June 1999
L. Gao, S. Shrivastava, H. Lee and G. Sobelman, ``A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor,'' was accepted for presentation at the 1999 Symposium on Field-Programmable Custom Computing Machines (FCCM '99).
4. Trips:
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None.
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