Faculty Directory
Chris Hyung-il Kim
Assistant Professor
Education
- Ph.D., EE, 2004, Purdue University, West Lafayette, IN, United States
- M.S., BME, 2000, Seoul National University, Seoul, Korea
- B.S., EE, 1998, Seoul National University, Seoul, Korea
Contact Information
- 4-161 EECS
- Telephone: (612) 625-2346
- E-mail: chriskim
![[at]](/media/images/email3.gif)
- Research Group Web Site
Honors/Awards
- 2009 NSF CAREER Award
- 2008 McKnight Land-Grant Professorship Award
- 2008 3M Non-Tenured Faculty Award
- 2008 DAC/ISSCC Student Design Contest Winner (advisor)
- 2008 Samsung Humantech Thesis Award (advisor)
- 2006-2008 IBM Faculty Partnership Award
- 2005 IEEE Circuits and Systems Society Outstanding Young Author Award
Synopsis
My research focuses on the cooperative field of circuit/device and circuit/architecture design for high performance, low-power VLSI systems in the nanometer regime. By the year 2014, 5-10 billion transistors with 10-13 nm physical gate lengths will be integrated on a 500-700 mm2 chip using a high-volume manufacturing process. Scaling of silicon MOS transistors in the nanometer dimension will continue to trouble designers with issues such as leakage power, statistical variability, power delivery, interconnect, reliability, testing, quantum effects, etc. Yet unknown problems will arise as researchers seek for solutions to continue the historical rate of progress. Numerous research opportunities at all levels of design (circuit, device, architecture, software, system, CAD, assembly, etc.) will offer innovative solutions to extend Moore�s law beyond the year 2015.
Selected Publications
- . T. Kim, J. Liu, J. Keane, and C.H. Kim, "A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme", International Solid-State Circuits Conference (ISSCC), Feb.
- . J. Gu, H. Eom, and C.H. Kim, "A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping", VLSI Circuits Symposium, June.
- . J. Keane, S. Venketraman, P.Butzen, C.H. Kim, "An Array-based Test Circuits for Fully Automated Dielectric Breakdown Characterization", Custom Integrated Circuits Conference (CICC), Sept.